The invention relates to a method for polishing a semiconductor substrate by chemical mechanical planarization (CMP) to planarize metal interconnects.
CMP is used to planarize semiconductor substrates. In CMP, a polishing pad is pressed against the substrate and is moved across the surface of the substrate while an aqueous liquid polishing composition (also referred to as slurry) is provided between the polishing pad and the substrate. The CMP process is a combination of chemical action and mechanical action. Chemicals in the polishing composition carry out the chemical action while the necessary mechanical action is provided by the movement of the substrate against the polishing pad. Abrasive particles when present in the polishing slurry enhance the mechanical action. An oxidizer when present in the composition converts the metal on the substrate to oxide that is then removed by movement of the substrate against the polishing pad. A metal oxide sometimes serves as an element of a passivating layer. Thus formation of the metal oxide layer reduces the rate of metal removal during the polishing process.
A known polishing process by CMP removes excess metal from an underlying surface of the substrate, and polishes such surface to a smooth planar surface. The known polishing operation begins by polishing with a relatively high polishing pressure, for example, 5 psi, to remove excess metal at a relatively high removal rate, followed by polishing with a relatively reduced polishing pressure, for example, 3 psi, to remove a residual thin film of the excess metal from an underlying surface, and to polish the surface to a smooth polished planar surface.
Copper is a relatively soft metal in comparison to the substrate of the semiconductor wafer that usually is silica or another similar hard substrate. By using conventional polishing equipment and techniques, a copper line forming a copper circuit on a patterned wafer is typically polished more in the center than on the edges. This phenomenon is commonly known as dishing.
The metal in a trench or trough on the semiconductor substrate provides a metal line forming a metal circuit. One of the problems to be overcome is that the polishing operation tends to remove metal from each trench or trough, causing recessed dishing of such metal. Dishing is undesirable as it causes variations in the critical dimensions of the metal circuit. There is a requirement for a method to planarize semiconductor wafers' metal interconnects that provides effective metal removal rates and reduces the interconnects' dishing.